Power amplifier systems with load control

ABSTRACT

A power amplification system is provided comprising: a power amplifier circuit; an output power control circuit for providing a plurality of values of capacitance, and a balun coupled to the power amplifier circuit and to the output power control circuit. The output power control circuit includes at least one load control capacitor. Each of the at least one load control capacitors is coupled to a load control switch for regulating the current path to and/or from the corresponding capacitor to control the value of the capacitance provided by the output power control circuit. A wireless device comprising such a power amplification system is also provided. A wireless module comprising such a power amplification system is also provided.

INCORPORATION BY REFERENCE TO ANY PRIORITY APPLICATIONS

Any and all applications, if any, for which a foreign or domesticpriority claim is identified in the Application Data Sheet of thepresent application are hereby incorporated by reference under 37 CFR1.57.

FIELD OF THE INVENTION

The present disclosure generally relates to power amplifiers, andparticularly to power amplifier systems for RF applications.

BACKGROUND OF THE INVENTION

Radio-frequency (RF) communications devices and systems may comprise orbe connected to an antenna to transmit and receive signals. Such devicesand systems may also comprise additional components and circuitry forprocessing signals transmitted and received via the antenna. Forexample, RF communications devices and systems using a cellularstandard, a wireless local area network (WLAN) standard, and/or anyother suitable communication standard may comprise or be connected toone or more power amplifier for amplifying a signal transmitted orreceived via the antenna.

Such a power amplifier may be a push-pull amplifier used for envelopetracking. While a push-pull amplifier can be implemented for a number ofRF communication devices and systems, a need exists for a betteramplification system design to improve various parameters, such asrejection of second harmonics, lower power supply rail capacitance, andpower efficiency.

BRIEF SUMMARY OF THE INVENTION

The invention is defined by the claims. Optional features are detailedin the dependent claims.

According to a number of embodiments of a first aspect, a poweramplification system is provided, the power amplification systemcomprising: a power amplifier circuit; an output power control circuitfor providing a plurality of values of capacitance, and a balun coupledto the power amplifier circuit and to the output power control circuit.The output power control circuit comprises at least one load controlcapacitor. Each of the at least one load control capacitors is coupledto a load control switch for regulating the current path to and/or fromthe corresponding capacitor to control the value of the capacitanceprovided by the output power control circuit.

Optionally, the power amplifier circuit may a plurality of transistors.

Optionally, at least two of the transistors of the power amplifiercircuit may be differential transistors.

Optionally, the power amplifier circuit may comprise a push-pullamplifier.

Optionally, the balun may comprise a first coil having a first end and asecond end, the first end of the first coil being coupled to a firstdifferential transistor and the second end of the first coil beingcoupled to a second differential transistor.

Optionally, the first end of the first coil may be coupled to a drain ora collector of the first differential transistor and the second end ofthe first coil may be coupled to a drain or a collector of the seconddifferential transistor.

Optionally, the balun may comprise a second coil having a first end anda second end, the first end of the second coil being coupled to an RFoutput node and the second end of the second coil being coupled to aground.

Optionally, the second end of the second coil may be coupled to theground via one or more termination capacitors.

Optionally, at least one of the termination capacitors may be asurface-mount capacitor.

Optionally, the output power control circuit may be coupled with atleast one of the termination capacitors.

Optionally, at least one of the load control capacitors and at least oneof the termination capacitors may be connected in parallel.

Optionally, a capacitance of the balun may be dependent on one or moreof: the value of the termination capacitor of the balun, the value ofthe capacitance provided by the output power control circuit, whetherthe termination capacitor and the output power control circuit isconnected in parallel or in series, and whether the load control switchis on or off.

Optionally, the output power control circuit may provide low capacitancehaving a value close to zero when the load control switch is off.

Optionally, when the load control switch is off, the output powercontrol circuit may not provide additional capacitance to the balun, andthe power amplification system may have a load impedance value thatleads to a lower output power.

Optionally, when the load control switch is on, the output power controlcircuit may provide additional capacitance to the balun, causing a loadimpedance value to decrease and output power of the power amplificationsystem to increase to a higher output power.

Optionally, an output power of the power amplification system may meetPower Class 3 requirement, for example as specified by the 3GPPcommunication standard, when the load control switch is off.

Optionally, an output power of the power amplification system may meetPower Class 2 requirement, for example as specified by the 3GPPcommunication standard, when the load control switch is on.

Optionally, at least one of the load control capacitors may be asilicon-on-insulator capacitor.

Optionally, the output power control circuit may comprise a plurality ofload control switches and a plurality of load control capacitors, eachof the load control switches being coupled to one or more of the loadcontrol capacitors.

Optionally, the output power control circuit may be configured toprovide a plurality of capacitor values alongside the low capacitancehaving a value close to zero by controlling one or more of the loadcontrol switches.

Optionally, the load control switch may be a FET switch.

Optionally, the power amplification system may comprise and/or beconnected to one or more power amplifier components configured toprovide at least one of advanced power tracking and envelop tracking.

Optionally, one or more part of the output power control circuit may becontrolled by a CMOS control, the CMOS control being configured receiveband and/or power mode controls over a MIPI digital interface.

Optionally, at least one of the transistors may be a heterojunctionbipolar transistor.

Optionally, the power amplification system may comprise a frequencyresponse compensation circuit for providing a plurality of values ofcapacitance. The frequency response compensation circuit comprises atleast one tuning capacitor. Each of the at least one tuning capacitorsis coupled to a switch for regulating the current path to and/or fromthe corresponding capacitor to control the value of the capacitanceprovided by the frequency response compensation circuit. The frequencyresponse compensation circuit is coupled to at least two of thetransistors of the power amplifier circuit. The frequency responsecompensation circuit is configured to reduce variation over frequency ofa load impedance of the power amplification system.

According to a number of embodiments of the first aspect, a wirelessdevice comprising: a memory; a user interface; a baseband sub-system; atransceiver; a power management component; and a power amplificationsystem is also provided. The power amplification system comprises: apower amplifier circuit; an output power control circuit for providing aplurality of values of capacitance, and a balun coupled to the poweramplifier circuit and to the output power control circuit. The outputpower control circuit comprises at least one load control capacitor.Each of the at least one load control capacitors is coupled to a loadcontrol switch for regulating the current path to and/or from thecorresponding capacitor to control the value of the capacitance providedby the output power control circuit.

According to a number of embodiments of the first aspect, a wirelessmodule comprising: a packaging substrate; one or more surface-mountdevices; a duplexer assembly; a front-end power management integratedcircuit; a match component; an antenna switch module; and a poweramplifier assembly comprising a power amplification system is alsoprovided. The power amplification system comprises: a power amplifiercircuit; an output power control circuit for providing a plurality ofvalues of capacitance, and a balun coupled to the power amplifiercircuit and to the output power control circuit. The output powercontrol circuit comprises at least one load control capacitor. Each ofthe at least one load control capacitors is coupled to a load controlswitch for regulating the current path to and/or from the correspondingcapacitor to control the value of the capacitance provided by the outputpower control circuit.

According to a number of embodiments of a second aspect, a poweramplification system comprising: a power amplifier circuit, the poweramplifier circuit comprising a plurality of transistors; and a frequencyresponse compensation circuit for providing a plurality of values ofcapacitance is provided. The frequency response compensation circuitcomprises at least one tuning capacitor. Each of the at least one tuningcapacitors is coupled to a tuning switch for regulating the current pathto and/or from the corresponding capacitor to control the value of thecapacitance provided by the frequency response compensation circuit. Thefrequency response compensation circuit is coupled to at least two ofthe transistors of the power amplifier circuit. The frequency responsecompensation circuit is configured to reduce variation over frequency ofa load impedance of the power amplification system.

Optionally, at least two of the transistors of the power amplifiercircuit may be differential transistors.

Optionally, the power amplifier circuit may comprise a push-pullamplifier.

Optionally, the power amplifier circuit may comprise at least onecapacitor connected to at least two of the differential transistors.

Optionally, the capacitor connected to the differential transistors maybe connected to the drains or collectors of two of the differentialtransistors.

Optionally, the frequency response compensation circuit may be coupledwith at least one of the capacitors connected to at least two of thedifferential transistors.

Optionally, at least one of the tuning capacitors and at least one ofthe capacitor connected to at least two of the differential transistorsare connected in parallel.

Optionally, a capacitance of the power amplifier circuit may bedependent on one or more of: the value of the capacitor connecting atleast two of the differential transistors, the value of the capacitanceprovided by the frequency response compensation circuit, whether thecapacitor connected to at least two of the differential transistors andthe frequency response compensation circuit is connected in parallel orin series, and whether the tuning switch is on or off.

Optionally, the frequency response compensation circuit may provide lowcapacitance having a value close to zero when the tuning switch is off.

Optionally, when the tuning switch is off, the frequency responsecompensation circuit may not provide additional capacitance to the poweramplifier circuit, and the power amplifier circuit may have an impedancevalue that is suitable for operation at a higher frequency band.

Optionally, when the tuning switch is on, the frequency responsecompensation circuit may provide additional capacitance to the poweramplifier circuit that causes an on-resistance of the amplifier circuitat a lower frequency band to decrease and the PAE of the poweramplification system at the lower frequency band to increase.

Optionally, the frequency response compensation circuit may comprise aplurality of tuning switches and a plurality of tuning capacitors, eachof the tuning switches being coupled to one or more of the tuningcapacitors.

Optionally, the frequency response compensation circuit may beconfigured to provide a plurality of capacitor values alongside the lowcapacitance having a value close to zero by controlling one or more ofthe tuning switches.

Optionally, the tuning switch may be a FET switch.

Optionally, the power amplification system may comprise and/or beconnected to one or more power amplifier components configured toprovide at least one of advanced power tracking and envelop tracking.

Optionally, at least one of the transistors may be a heterojunctionbipolar transistor.

Optionally, one or more part of the frequency response compensationcircuit may be controlled by a CMOS control, the CMOS control beingconfigured receive band and/or power mode controls over a MIPI digitalinterface.

Optionally, the power amplification system may comprise an output powercontrol circuit for providing a plurality of values of capacitance; anda balun coupled to the power amplifier circuit and to the output powercontrol circuit. The output power control circuit comprises at least oneload control capacitor. Each of the at least one load control capacitorsis coupled to a load control switch for regulating the current path toand/or from the corresponding capacitor to control the value of thecapacitance provided by the output power control circuit.

According to a number of embodiments of the second aspect, a wirelessdevice comprising: a memory; a user interface; a baseband sub-system; atransceiver; a power management component; and a power amplificationsystem is also provided. The power amplification system comprises: apower amplifier circuit, the power amplifier circuit comprising aplurality of transistors; and a frequency response compensation circuitfor providing a plurality of values of capacitance is provided. Thefrequency response compensation circuit comprises at least one tuningcapacitor. Each of the at least one tuning capacitors is coupled to atuning switch for regulating the current path to and/or from thecorresponding capacitor to control the value of the capacitance providedby the frequency response compensation circuit. The frequency responsecompensation circuit is coupled to at least two of the transistors ofthe power amplifier circuit. The frequency response compensation circuitis configured to reduce variation over frequency of a load impedance ofthe power amplification system.

According to a number of embodiments of the second aspect, a wirelessmodule comprising: A packaging substrate; one or more surface-mountdevices; a duplexer assembly; a front-end power management integratedcircuit; a match component; an antenna switch module; and a poweramplifier assembly comprising a power amplification system is alsoprovided. The power amplification system comprises: a power amplifiercircuit, the power amplifier circuit comprising a plurality oftransistors; and a frequency response compensation circuit for providinga plurality of values of capacitance is provided. The frequency responsecompensation circuit comprises at least one tuning capacitor. Each ofthe at least one tuning capacitors is coupled to a tuning switch forregulating the current path to and/or from the corresponding capacitorto control the value of the capacitance provided by the frequencyresponse compensation circuit. The frequency response compensationcircuit is coupled to at least two of the transistors of the poweramplifier circuit. The frequency response compensation circuit isconfigured to reduce variation over frequency of a load impedance of thepower amplification system.

The first aspect and second aspect, and any optional features of either,may be combined into a common power amplifier. Such a power amplifiermay provide PAE improvement by headroom reduction and PAE bandwidthenhancement across operational frequency.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in more detail, by way of example, withreference to the accompanying drawings, in which:

FIG. 1 illustrates an example wireless system or architecture, accordingto an embodiment;

FIG. 2 illustrates an example amplification system comprising a radiofrequency (RF) amplifier assembly having one or more power amplifiers,according to an embodiment;

FIGS. 3A to 3E illustrate non-limiting examples of power amplifiers, inaccordance with a number of embodiments;

FIG. 4 illustrates an example amplification system implemented as ahigh-voltage (HV) power amplification system, according to anembodiment;

FIG. 5 illustrates an example power amplification system comprising anamplifier circuit, frequency response compensation circuit, transformerbalun, and an output power control circuit, according to an embodiment;

FIG. 6 illustrates a circuit diagram of an example power amplificationsystem comprising an amplifier circuit, frequency response compensationcircuit, transformer balun, and an output power control circuit,according to an embodiment;

FIG. 7A is an exemplary graph illustrating how power-added efficiency(PAE) variation over frequency changes depending on the value of atermination capacitor of a balun when a load control switch is off,according to an embodiment;

FIG. 7B is an exemplary graph illustrating how PAE variation overfrequency changes depending on the value of a termination capacitor(852) of a balun (519) when a load control switch (856) is on, accordingto an embodiment;

FIG. 8A is an exemplary Smith Chart according to an embodiment;

FIG. 8B is an exemplary Smith Chart according to an embodiment;

FIG. 9A is an exemplary graph illustrating how a power amplifier loadimpedance changes over frequency in an exemplary power amplifier systemwithout an output power control circuit, according to an embodiment;

FIG. 9B is an exemplary graph illustrating how a power amplifier loadimpedance changes over frequency in an exemplary power amplifier systemwith an output power control circuit, according to an embodiment;

FIG. 10 is an exemplary graph illustrating PAE variation over frequencyaccording to an embodiment;

FIG. 11 illustrates an example wireless module according to anembodiment;

FIG. 12 illustrates an example wireless device according to anembodiment; and

FIG. 13 is an exemplary graph illustrating PAE variation over outputpower of an exemplary power amplifier configured to support frequencybands that need to operate at different power levels.

DETAILED DESCRIPTION OF EMBODIMENTS

The embodiments disclosed herein generally relate to power amplifiersfor RF communication applications. In accordance with someimplementations, the present disclosure relates to a power amplificationsystem. The power amplification system comprises a power amplifiercircuit comprising a balun. Although the power amplification systemillustrated in the examples of [0059] FIG. 5 and [0060] FIG. 6 comprisesa push-pull amplifier comprising a transformer balun, the amplificationsystem may comprise any other suitable type of power amplifiercomprising any other suitable type of transformer balun. The poweramplification system may also comprise an output power control circuitcoupled to the balun, the output power control circuit being configuredto provide a plurality of values of capacitance to control the outputpower of power amplifier. The power amplification system may alsocomprise a frequency response compensation circuit coupled to at leasttwo of the transistors of the power amplifier circuit to reducevariation over frequency of a load impedance of the power amplificationsystem. The power amplification system illustrated in the examples of[0059]FIG. 5 and [0060] FIG. 6 comprises both the output power controlcircuit and the frequency response compensation circuit. However, inother embodiments, The power amplification system may comprise only oneof the output power control circuit and the frequency responsecompensation circuit.

Referring to [0055] FIG. 1 , embodiments of the present invention maygenerally be implemented in a wireless system or architecture (50)having an amplification system (52). The amplification system (52) maybe implemented as one or more devices, and such device(s) can beutilized in the wireless system/architecture (50). The wirelesssystem/architecture (50) may be implemented in, for example, a portablewireless device. Examples of such a wireless device are described hereinwith respect to FIG. 12 .

FIG. 2 shows that the amplification system (52) of [0055]FIG. 1typically comprises a radio-frequency (RF) amplifier assembly (54)having one or more power amplifiers (PAs). In the example of [0056] FIG.2 , three PAs (60 a-60 c) are depicted as forming the RF amplifierassembly (54). It will be understood that other numbers of PA(s) canalso be implemented. It will also be understood that one or morefeatures of the present disclosure can also be implemented in RFamplifier assemblies having other types of RF amplifiers.

The RF amplifier assembly (54) may be implemented on one or moresemiconductor die, and such die can be included in a packaged modulesuch as a power amplifier module (PAM) or a front-end module (FEM). Sucha packaged module is typically mounted on a circuit board associatedwith, for example, a portable wireless device.

The PAs (e.g., 60 a-60 c) in the amplification system (52) may be biasedby a bias system (56). Further, supply voltages for the PAs may beprovided by a supply system (58). Either or both of the bias system (56)and the supply system (58) may be included in the foregoing packagedmodule having the RF amplifier assembly (54).

The amplification system (52) may include a matching network (62). Sucha matching network may be configured to provide input matching and/oroutput matching functionalities for the RF amplifier assembly (54).

For the purpose of description, it will be understood that each PA (60)of [0056] FIG. 2 may be implemented in a number of ways. [0057]FIG.3A-[0057] FIG. 3E show non-limiting examples of how such a PA may beconfigured. [0057] FIG. 3A shows an example amplifying transistor (64)that can form a part of PA, where an input RF signal (RF_in) is providedto a base of the transistor (64), and an amplified RF signal (RF_out) isoutput through a collector of the transistor (64). A plurality of suchamplifying transistors may be included in a PA.

[0057] FIG. 3B shows an example PA having a plurality of amplifyingtransistors (e.g., 64 a, 64 b) arranged in stages. An input RF signal(RF_in) is provided to a base of the first transistor (64 a), and anamplified RF signal from the first transistor (64) a is output throughits collector. The amplified RF signal from the first transistor (64 a)is provided to a base of the second transistor (64 b), and an amplifiedRF signal from the second transistor (64 b) is output through itscollector to thereby yield an output RF signal (RF_out) of the PA.

The foregoing example PA configuration of [0057] FIG. 3B can be depictedas two or more stages as shown in [0057] FIG. 3C. The first stage (64) amay be configured as, for example, a driver stage; and the second stage(64 b) may be configured as, for example, an output stage.

[0057] FIG. 3D shows that in some embodiments, a PA may be configured asa Doherty PA. Such a Doherty PA may include amplifying transistors (64a, 64 b) configured to provide carrier amplification and peakingamplification of an input RF signal (RF_in) to yield an amplified outputRF signal (RF_out). The input RF signal may be split into the carrierportion and the peaking portion by a splitter. The amplified carrier andpeaking signals may be combined to yield the output RF signal by acombiner.

[0057] FIG. 3E shows that in some embodiments, a PA may be implementedin a cascode configuration. An input RF signal (RF_in) may be providedto a base of the first amplifying transistor (64) a operated as a commonemitter device. The output of the first amplifying transistor (64 a) maybe provided through its collector and be provided to an emitter of thesecond amplifying transistor (64 b) operated as a common base device.The output of the second amplifying transistor (64 b) may be providedthrough its collector so as to yield an amplified output RF signal(RF_out) of the PA.

In the various examples of [0057] FIGS. 3A-[0057] FIGS. 3E, theamplifying transistors are described as bipolar junction transistors(BJTs) such as heterojunction bipolar transistors (HBTs). It will beunderstood that one or more features of the present disclosure may alsobe implemented in or with other types of transistors such asfield-effect transistors (FETs). For simplicity, throughout thedisclosure, a “gate” or a “base” of a transistor will be referred to asa “base”, a “drain” or a “collector” of a transistor will be referred toas a “collector”, and a “source” or an “emitter” will be referred to asa “emitter”.

FIG. 4 shows that in some embodiments, the amplification system (52) of[0056] FIG. 2 may be implemented as a high-voltage (HV) poweramplification system (100). Such a system may include an HV poweramplifier assembly (54) configured to include HV amplification operationof some or all of the PAs (e.g., 60 a-60 c). As described herein, suchPAs may be biased by a bias system (56). The foregoing HV amplificationoperation may be facilitated by an HV supply system (58). An interfacesystem (72) may be implemented to provide interface functionalitiesbetween the HV power amplifier assembly (54) and either or both of thebias system (56) and the HV supply system 58.

For the purpose of description, it will be understood that high-voltage(HV) can include voltage values that are higher than a battery voltageutilized in portable wireless devices. For example, an HV can be greaterthan 3.7V or 4.2V. In some situations, an HV can include voltage valuesthat are greater than a battery voltage and at which portable wirelessdevices can operate more efficiently. In some situations, an HV caninclude voltage values that are greater than a battery voltage and lessthan a breakdown voltage associated with a given type of PA. In theexample context of GaAs heterojunction bipolar transistor (HBT), such abreakdown voltage can be in a range of 15V to 25V. Accordingly, an HVfor GaAs HBT PA can be in a range of, for example, 3.7V to 25V, 4.2V to20V, 5V to 15V, 6V to 14V, 7V to 13V, or 8V to 12V.

Disclosed are examples related to use of a push-pull amplifier includinga transformer balun. It will be understood that, although the poweramplification system (500) illustrated in the examples of [0059] FIG. 5comprises a push-pull amplifier circuit (510 and a transformer balun(519), in other embodiments, the amplification system (500) may compriseany other suitable type of power amplifier (510) comprising any othersuitable type of transformer balun (519).

[0059] FIG. 5 illustrates an exemplary power amplification system (500)comprising a push-pull amplifier circuit (510), a frequency responsecompensation circuit (511), a balun (519) (e.g. transformer balun), anda output power control circuit (520). The frequency responsecompensation circuit (511), in the example shown [0059]FIG. 5 , isincluded in the amplifier circuit (510). However, in other embodiments,the frequency response compensation circuit (511) may form a part ofanother part of the power amplification system (500) that is not theamplifier circuit (510), or the frequency response compensation circuit(511) may be a separate part within the power amplification system(500). Similarly, the balun (519), in the example shown [0059]FIG. 5 ,is not included in the amplifier circuit (510). However, in otherembodiments, the balun (519) may form a part of the amplifier circuit(510) or another part of the power amplification system (500).

The power amplification system (500) of [0059] FIG. 5 is configured toamplify an input radio-frequency (RF) signal (RFin) received at an inputnode (501) to generate an output RF signal (RFout) at an output node(502). The output power control circuit (520) is configured to providetwo or more values of capacitance. One of the capacitance values thatthe output power control circuit (520) can provide may be a low valueclose to zero (in the case of open circuit). As the output power controlcircuit (520) is coupled to the balun (519), changing the capacitancevalue provided by the output power control circuit (520) leads to achange of a capacitance value of the balun (519). The balun (519) maycomprise a termination capacitor (852). In such cases, the output powercontrol circuit (520) may be coupled to the termination capacitor (582)of the balun (519). In such cases, the total termination capacitance ofthe balun (519) is determined by: the value of the termination capacitor(852) of the balun (519), the capacitance value provided by the powercontrol circuit (520), and the manner in which the termination capacitor(852) of the balun (519) and the power control circuit (520) areconnected (e.g. in parallel or in series). Consequently, switching thecapacitance value of the power control circuit (520) enables control ofthe total termination capacitance of the balun (519), which in turnenables load line control. The switching of the capacitance value of thepower control circuit (520) will be discussed further with respect to[0060]FIG. 6 .

[0070] FIG. 13 illustrates power-added efficiency (PAE) variation overoutput power of an exemplary power amplifier configured to supportfrequency bands that need to operate at different power levels. Inparticular, [0070] FIG. 13 shows variation over output power for a poweramplifier that needs to operate at both Power Class 2 (PC2) and PowerClass 3 (PC3) power levels specified by the 3GPP communication standard.In such a case, PC2 requirement sets the maximum power of the powerneeds because PC2 requires higher output power than PC3. However, thisdecreases the PAE of the amplifier during PC3 band operation because thepower amplifier would still be operating with the maximum output powerset by the PC2 requirement. For example, as shown in [0070] FIG. 13 ,the power amplifier may have a suitable level of headroom of ˜6 dBduring PC2 operation, leading to PAE of ˜50% with 80% trackerefficiency, and ˜62% with 100% tracker efficiency. However, the poweramplifier may have an excessive level of headroom of 8-9 dB during PC3operation, leading to significantly decreased PAE of ˜44% with 80%tracker efficiency, and ˜54% with 100% tracker efficiency.

The output power control circuit (520) of [0059] FIG. 5 can beparticularly useful for improving the power-added efficiency (PAE) ofthe power amplification system (500) when the power amplification system(500) is configured to accommodate two or more bands of frequenciesand/or power modes as shown in the example of [0070] FIG. 13 . Theimprovement of the PAE is achieved by adjusting the output power, bycontrolling the capacitance provided by the output power control circuit(520), according to the output power requirements set by the frequencyband of operation. This can minimize unnecessary output power headroom,particularly when the frequency band of operation requires lower outputpower from the power amplification system (500). The PAE improvementachieved by output power control circuit (520) will be discussed furtherwith respect to [0061] FIG. 7 -[0065] FIG. 9

The frequency response compensation circuit (511) is configured toreduce variation over frequency of a number of metrics of the poweramplification system (500). For example, the frequency responsecompensation circuit (511) reduces variation over frequency of a loadimpedance of the power amplification system (500). The frequencyresponse compensation circuit (511) is configured to provide two or morevalues of capacitance. One of the capacitance values that the frequencyresponse compensation circuit (511) can provide may be a low value closeto zero. The low value that the frequency response compensation circuit(511) can provide may be determined and/or optimized based on a tradeoffbetween the on-resistance and off-capacitance of the tuning switch(866). Generally, lower off-capacitance of the tuning switch (866) leadsto higher on-resistance of the tuning switch (866), and higheron-resistance of the tuning switch (866) may lead to degradation of thePAE of the power amplification system (500) when the tuning switch (866)is on. The frequency response compensation circuit (511) is coupled toat least two of the transistors of the amplifier circuit (510). As aresult, changing the capacitance value provided by the frequencyresponse compensation circuit (511) leads to a change of a capacitancevalue of the amplifier circuit (510). For example, the frequencyresponse compensation circuit (511) may be connected to a collector or aemitter of a first transistor (843) of the amplifier circuit (510) and acollector or a emitter a second transistor (842) of the amplifiercircuit (510). The amplifier circuit (510) may optionally comprise acapacitor (862) connecting two of the transistors (842, 843) of theamplifier circuit (510). In such cases, the frequency responsecompensation circuit (511) may be coupled to the capacitor (862)connecting the two of the transistors (842, 843). In such cases, thetotal capacitance of the amplifier circuit (510) is dependent on: thevalue of the capacitor (862) connecting the two of the transistors (842,843) of the amplifier circuit (510), the capacitance value provided bythe frequency response compensation circuit (511), and the manner inwhich the capacitor (862) connecting the two of the transistors (842,843) and the frequency response compensation circuit (511) are connected(e.g. in parallel or in series). Consequently, switching the capacitancevalue of the frequency response compensation circuit (511) enablescontrol of the total capacitance of the amplifier circuit (510), whichin turn enables adjustment of reactance of the amplifier circuit (510).The switching of the capacitance value of the frequency responsecompensation circuit (511) will be discussed further with respect to[0060]FIG. 6 .

The frequency response compensation circuit (511) can be particularlyuseful for improving the PAE of the power amplification system (500)when the power amplification system (500) is configured to accommodate awide bandwidth of frequencies. The improvement of the PAE is achieved byadjusting the reactance of the amplifier circuit (510), by controllingthe capacitance provided by the frequency response compensation circuit(511), according to the frequency band of operation. This can reducevariation over frequency of the PAE and/or the saturated output power(Psat) of the power amplification system (500), particularly at lowerfrequencies. The PAE improvement achieved by output power controlcircuit (520) will be discussed further with respect to FIG. 9B is anexemplary graph illustrating how a power amplifier load impedancechanges over frequency in an exemplary power amplifier system with anoutput power control circuit, according to an embodiment.

The power amplification system (500) of [0059] FIG. 5 optionallycomprises a bias system (56) configured to provide a bias voltage to oneor more transistors of the power amplification system (500), and asupply system (58) configured to provide a supply voltage to theamplifier circuit (510). In the example shown [0059]FIG. 5 , the biassystem (56) and the supply system (58) are not included in the amplifiercircuit (510). However, in other embodiments, at least one of the biassystem (56) and the supply system (58) may form a part of the amplifiercircuit (510) or other part of the power amplification system (500).Alternatively, the bias system (56) and the supply system (58) may belocated outside the power amplification system (500). The amplifiercircuit (510) may be or may comprise a push-pull amplifier (510).

The power amplifier circuit (510) can be or comprise any of the poweramplifiers described above with respect to [0057] FIGS. 3A-[0057] FIG.3E, a push-pull amplifier, or any other type of power amplifier. Thepower amplifier circuit (510) comprises an amplifier element configuredto amplify the RF signal. The amplifier element may include, forexample, one or more transistors. The amplifier element may be poweredby a supply voltage (V_(CC)) and include a connection to a groundvoltage. The supply voltage (V_(CC)) may be provided by the supplysystem (58).

[0060] FIG. 6 illustrates a circuit diagram of an exemplary poweramplification system (500) comprising a push-pull amplifier circuit(510), a frequency response compensation circuit (511), a balun (519)(e.g. transformer balun), and an output power control circuit (520). Thepower amplification system (500) is configured to amplify an inputradio-frequency (RF) signal (RFin) received at an input node (801) togenerate an output RF signal (RFout) at an output node (802).

The power amplification system (500) may comprise one or more drivetransistors. The power amplification system (500) may comprise a firstcapacitor (821), a second capacitor (822) coupled in series between theinput node (801) and the base of at least one of the drive transistor.The power amplification system (500) may comprise a first inductor (831)having a first end coupled to a node between the first capacitor (821)and the second capacitor (822) and having a second end coupled to aground voltage. The power amplification system (500) may comprise or beconnected to a drive bias circuit powered by a supply voltage (Vcc). Thedrive bias circuit may be coupled to the base of the one or more drivetransistors and configured to bias the drive transistor.

The power amplification system (500) may comprise a transformer divider(870). The transformer divider (870) may comprise a first coil and asecond coil. A first end of the first coil may be coupled to thecollector of the one or more drive transistors and a second end of thefirst coil may be coupled to the ground voltage via a capacitor. Thefirst end and second end of the second coil may be coupled, viarespective capacitors, to respective bases of respective differentialtransistors (842, 843). Although each of the first end and second end ofthe second coil in the example of [0060] FIG. 6 is coupled to onedifferential transistor (842, 843), in other embodiments, at least oneof the first end and second end of the second coil may be coupled to twoor more differential transistors (842, 843).

The power amplification system (500) comprises a balun (519). Althoughthe balun (519) in the example of [0060] FIG. 6 is a transformer balun(519), in other embodiments the balun (519) may be any suitable type ofbalun (519). The balun (519) may comprise a first coil (881) (e.g. aprimary coil) and a second coil (882) (e.g. a secondary coil). In suchcases, each of the first and second coils (881, 882) comprises a firstend and a second end. The first and second ends of the first coil (881)are respectively coupled to the collectors of the differentialtransistors (842, 843). The second end of the second coil (882) iscoupled to the ground voltage via a termination capacitor (852). Thetermination capacitor (852) in the example of [0060] FIG. 6 isoptionally a surface-mount capacitor (CSMT). However, in otherembodiments the termination capacitor (852) may be any other type ofcapacitor, such as a silicon-on-insulator (SOI) capacitor or ametal-oxide-semiconductor (MOS) capacitor. The first end of the secondcoil (882) is coupled to an RF output node (802). Optionally, the balun(519) may be an integrated passive device (IPD) balun.

The power amplification system (500) comprises a frequency responsecompensation circuit (511) coupled to the differential transistors (842,843). As shown in the example of [0060] FIG. 6 , the frequency responsecompensation circuit (511) may comprise a first tuning capacitor (864A),a tuning switch (866), and a second tuning capacitor (864B) connected inseries. The first tuning capacitor (864A) may be coupled to thecollector of the first differential transistor (843), the second tuningcapacitor (864B) may be coupled to the second differential transistor,and the tuning switch (866) may connect the first and second tuningcapacitors (864A, 864B). As shown in the example of FIG. 6 , theamplifier circuit (510) may optionally also comprise a capacitor (862)connecting the collectors of the differential transistors (842, 843). Insuch cases, the frequency response compensation circuit (511) may becoupled to the capacitor (862) connecting the two differentialtransistors (842, 843). The tuning switch (866) may be any suitabletypes of switch that can provide on and off modes, such as a FET switch.

When the tuning switch (866) is on, the frequency response compensationcircuit (511) connects the tuning capacitor(s) (864A, 864B) to theamplifier circuit (510) to provide additional capacitance. On the otherhand, when the tuning switch (866) is off, the frequency responsecompensation circuit (511) forms an open circuit, therefore, thefrequency response compensation circuit (511) has no influence on thecapacitance of the amplifier circuit (510). In the example of [0060]FIG. 6 , when the tuning switch (866) is off, the capacitance betweenthe collectors of the first and second differential transistors (842,843) is equal to the value of the capacitor (862) connecting thecollectors of the first and second differential transistors (842, 843).On the other hand, when the tuning switch (866) is on, the capacitancebetween the collectors of the first and second differential transistors(842, 843) is equal to:

$C_{1} + \frac{1}{\frac{1}{C_{{diff}\_ A}} + \frac{1}{C_{{diff}\_ B}}}$

wherein C₁ is the value of the capacitor (862) connecting the collectorsof the first and second differential transistors (842, 843), C_(diff,A)is the value of the first tuning capacitor (864A), and C_(diff,B) is thevalue of the second tuning capacitor (864B).

Although in the example of [0060] FIG. 6 , the frequency responsecompensation circuit (511) comprises two tuning capacitors (864A, 864B)and one tuning switch (866), in other embodiments the frequency responsecompensation circuit (511) may comprise any number of tuningcapacitor(s) (864A, 864B) and any number of tuning switch(es) (866)connected in series or parallel. For example, the frequency responsecompensation circuit (511) may only comprise one tuning capacitor andone tuning switch (866). In such a case, the capacitance between thecollectors of the first and second differential transistors (842, 843)is equal to:

C₁+C_(diff)

wherein C₁ is the value of the capacitor (862) connecting the collectorsof the first and second differential transistors (842, 843) and C_(diff)is the value of the one tuning capacitor (864A).

It will be understood that, in other embodiments, the capacitor (862)connecting the first and second differential transistors (842, 843)and/or the frequency response compensation circuit (511) may beconnected to other parts of the first and second differentialtransistors (842, 843), such as the emitters, instead of the collectors.It will also be understood that, in other embodiments, the poweramplification system (500) may not comprise the capacitor (862)connecting the first and second differential transistors (842, 843). Insuch cases, the capacitance between the collectors of the first andsecond differential transistors (842, 843) is equal to the capacitancevalue of the frequency response compensation circuit (511).

The frequency response compensation circuit (511) may optionallycomprise a plurality of tuning switches. In such cases, each of thetuning switches may be coupled to one or more tuning capacitors. Suchconfigurations enables the frequency response compensation circuit (511)to provide a plurality of capacitance values alongside the lowcapacitance having a value close to zero (in the case of open circuit).

Having such a frequency response compensation circuit (511) in the poweramplification system (500) can be particularly useful for improving thePAE of the power amplification system (500) when the power amplificationsystem (500) is configured to accommodate a wide bandwidth offrequencies. The improvement of the PAE is achieved by adjusting thereactance of the amplifier circuit (510), by controlling the capacitanceprovided by the frequency response compensation circuit (511), accordingto the frequency band of operation. This can reduce variation overfrequency of the PAE and/or the saturated output power (Psat) of thepower amplification system (500), particularly at lower frequencies.

[0066] [0065] FIG. 9B is an exemplary graph illustrating how a poweramplifier load impedance changes over frequency in an exemplary poweramplifier system with an output power control circuit, according to anembodiment;

FIG. 10 is a graph showing an exemplary PAE variation over frequency.Reactance is generally inversely proportional to both capacitance andfrequency. In the example of [0066] [0065] FIG. 9B is an exemplary graphillustrating how a power amplifier load impedance changes over frequencyin an exemplary power amplifier system with an output power controlcircuit, according to an embodiment;

FIG. 10 , the on-resistance (R_(ON)) of the tuning switch (866) has ahigh value of ˜1Ω when additional tuning capacitor(s) (864A, 864B) arenot connected to the amplifier circuit (510) (i.e. the tuning switch(866) is off). On the other hand, the R_(ON) of the tuning switch (866)has a low value close to 0 Ω when additional tuning capacitor(s) (864A,864B) are connected to the amplifier circuit (510) (i.e. the tuningswitch (866) is on). It can be seen from [0066] [0065] FIG. 9B is anexemplary graph illustrating how a power amplifier load impedancechanges over frequency in an exemplary power amplifier system with anoutput power control circuit, according to an embodiment;

FIG. 10 that, when the tuning switch (866) is off (R_(ON)≈1), the poweramplification system (500) suffers from PAE reduction at lowerfrequencies. This can be attributed to higher reactance at lowerfrequency. Such losses of PAE can be compensated by connecting theadditional tuning capacitor(s) (864A, 864B) to the amplifier circuit(510) by turning the tuning switch (866) on. [0066] [0065] FIG. 9B is anexemplary graph illustrating how a power amplifier load impedancechanges over frequency in an exemplary power amplifier system with anoutput power control circuit, according to an embodiment;

FIG. 10 also illustrates an exemplary PAE variation over frequency (MCMSHORT) for a hypothetical scenario wherein the tuning switch (866) is aperfect switch having zero R_(ON).

The power amplification system (500) comprises an output power controlcircuit (511) coupled to the balun (519). As shown in the example of[0060]FIG. 6 , the output power control circuit (511) may comprise aload control capacitor (854), and a load control switch (856) connectedin series. The load control capacitor (854) may be coupled to the secondend of the second coil (882) of the balun (519), and the load controlcapacitor (854) may be coupled to the ground voltage via the loadcontrol switch (856). Alternatively, in other embodiments, the loadcontrol switch (856) may be coupled to the second end of the second coil(882) of the balun (519), and the load control switch (856) may becoupled to the ground voltage via the load control capacitor (854). Asshown in the example of [0060] FIG. 6 , the balun (519) may comprise atermination capacitor (852) connecting the second end of the second coil(882) of the balun (519) to the ground voltage. In such cases, outputpower control circuit (511) may be coupled to the termination capacitor(852). The load control capacitor (854) in the example of [0060] FIG. 6is optionally a silicon-on-insulator (SOI) capacitor (CSOI). However, inother embodiments the load control capacitor (854) may be any other typeof capacitor, such as a surface-mount capacitor (CSMT) or ametal-oxide-semiconductor (MOS) capacitor. The load control switch (856)may be any suitable types of switch that can provide on and off modes,such as a FET switch.

When the load control switch (856) is on, the output power controlcircuit (511) connects the load control capacitor (854) to the balun(519) to provide additional capacitance. On the other hand, when theload control switch (856) is off, the output power control circuit (511)forms an open circuit, therefore, the output power control circuit (511)has no influence on the capacitance of the balun (519). In the exampleof [0060]

FIG. 6 , when the load control switch (856) is off, the capacitancebetween the second end of the second coil (882) of the balun (519) andthe ground is equal to the value of the termination capacitor (852),C_(SMT). On the other hand, when the load control switch (856) is on,the capacitance between the second end of the second coil (882) of thebalun (519) and the ground is equal to:

C_(SMT)+C_(SOI)

wherein C_(SMT) is the termination capacitor (852) and C_(SOI) is thevalue of the load control capacitor (856).

Although in the example of [0060] FIG. 6 , the output power controlcircuit (511) comprises one load control capacitor (854) and one loadcontrol switch (856), in other embodiments the output power controlcircuit (511) may comprise any number of load control capacitors andload control switch(es).

It will be understood that, in other embodiments, the terminationcapacitor (852) and/or the output power control circuit (511) may beconnected to other parts of the balun (519), such as a node locatedbetween the first and second ends of the second coil (882), instead ofthe second end of the second coil (882). It will also be understoodthat, in other embodiments, the balun (519) may not comprise thetermination capacitor (852). In such cases, the capacitance between thebalun (519) and the ground is equal to the capacitance value of theoutput power control circuit (511).

The output power control circuit (511) may optionally comprise aplurality of load control switches. In such cases, each of the loadcontrol switches may be coupled to one or more load control capacitors.Such configurations enable the output power control circuit (511) toprovide a plurality of capacitance values alongside the low capacitancehaving a value close to zero (in the case of open circuit).

The output power control circuit (520) can be particularly useful forimproving the PAE of the power amplification system (500) when the poweramplification system (500) is configured to accommodate two or morebands of frequencies and/or power modes. The improvement of the PAE isachieved by adjusting the output power, by controlling the capacitanceprovided by the output power control circuit (520), according to theoutput power requirements set by the frequency band of operation. Thiscan minimize unnecessary output power headroom, particularly when thefrequency band of operation requires lower output power from the poweramplification system (500).

[0061] FIG. 7A is an exemplary graph illustrating how PAE variation overfrequency changes depending on the value of the termination capacitor(852) of the balun (519) when the load control switch (856) is off. Asone mode of operation (e.g. PC3 operation) requires lower output powerthan another mode of operation (e.g. PC2 operation), it may bepreferable to decrease the capacitance of the balun (519). Thecapacitance of the balun (519) may be decreased by turning off the loadcontrol switch (856) and optionally replacing the termination capacitor(852) of the balun (519) with a capacitor having a lower value.

However, decreasing the capacitance of the balun can be problematic forhigher power operation, such as PC2 operation which requires higheroutput power than PC3 operation. The output power control circuit (520)can be particularly useful in such cases, as it can provide additionalcapacitor(s) that can be connected to and disconnected from the balun(519) depending on the required output power. [0061]

FIG. 7B is an exemplary graph illustrating how PAE variation overfrequency changes depending on the value of the termination capacitor(852) of the balun (519) when the load control switch (856) is on. Inthis case, for PC2 operation, the output power control circuit (520) canprovide additional capacitance to the balun (519) in addition to theoptimal capacitance value of the balun (519) for PC3 operation.

[0065] FIG. 9A illustrates how the power amplifier load impedancechanges over frequency in an exemplary power amplifier system withoutthe output power control circuit (520). The graph shows that the loadimpedance is inversely proportional to the frequency. [0063] FIG. 8Aillustrates a corresponding Smith Chart, showing that the output powerof the amplifier system without the output power control circuit (520)is not adapted depending on the band of frequencies and/or power modes.

On the other hand, [0065] FIG. 9B illustrates how the power amplifierload impedance changes over frequency in an exemplary power amplifiersystem with the output power control circuit (520). Unlike the exampleof [0065] FIG. 9A and [0063] FIG. 8A, the output power control circuit(520) enables the load impedance to be increased for PC3 band anddecreased for PC2 band. In the example shown in [0065] FIG. 9B, theswitching of the output power control circuit (520) takes place at ˜2570Hz. [0063] FIG. 8B illustrates a corresponding Smith Chart, showing thatthe output power of the amplifier system with the output power controlcircuit (520) is adapted depending on the band of frequencies and/orpower modes.

Using the output power control circuit (520) in this way can provide aneasy way to switch between a plurality of selectable capacitance valuesof the balun (519) depending on the required output power.

Whilst the output power control circuit (520) has been described, inrelation to [0059]FIG. 5 and [0060] FIG. 6 , as being provided incombination with the frequency response compensation circuit (511), thisis not required. Either can be implemented alone without the other. Thatis, embodiments of the power amplification system (500) that areimplemented without the frequency response compensation circuit (511)may not comprise the one or more of the parts and/or components shown in[0059]FIG. 5 and/or [0060] FIG. 6 , including: the tuning capacitor(s)(864A, 864B), the tuning switch (866), and the capacitor (862)connecting two of the transistors (842, 843). Similarly, embodiments ofthe power amplification system (500) that are implemented without theoutput power control circuit (520) may not comprise the one or more ofthe parts and/or components shown in [0059] FIG. 5 and/or [0060]FIG. 6 ,including: the load control capacitor (854), the load control switch(856), and the balun (519) or one or more parts of the balun (519) suchas the termination capacitor (852) connecting the second coil (882) ofthe balun (519) to the ground.

In embodiments of the power amplification system (500) that areimplemented with both the output power control circuit (520) and thefrequency response compensation circuit (511), such as the poweramplification system (500) according to [0059] FIG. 5 and [0060] FIG. 6, the features and advantages of the output power control circuit (520)and the frequency response compensation circuit (511) may be cooperatedin a synergistic manner to allow effective PAE improvement over anextended bandwidth. As discussed with respect to [0061] FIG. 7 , [0063]FIG. 8 , [0065] FIG. 9 and [0070] FIG. 13 , the output power controlcircuit (520) improves PAE by minimizing unnecessary power headroom,whereas, as discussed with respect to [0066][0065] FIG. 9B is anexemplary graph illustrating how a power amplifier load impedancechanges over frequency in an exemplary power amplifier system with anoutput power control circuit, according to an embodiment;

FIG. 10 , the frequency response compensation circuit (511) improves PAEacross extended bandwidth. In other words, the output power controlcircuit (520) controls the real part of the load impedance which affectsthe output power of the power amplification system (500), and thefrequency response compensation circuit (511) controls the imaginarypart of the load impedance which affects the frequency response of thepower amplification system (500). Therefore, the combination of theoutput power control circuit (520) and the frequency responsecompensation circuit (511) can synergistically improve the parameters ofthe power amplification system (500) that are dependent on both the realand imaginary parts of the load impedance, such as PAE. Furthermore,combining the output power control circuit (520) and the frequencyresponse compensation circuit (511) can provide PAE enhancement acrossextended bandwidth at the same time as meeting various requirements setby size constraints of the power amplification system (500) and/ordevices comprising the power amplification system (500).

One or more advantageous features of the power amplification system(500) described herein may be combined with one or more other types ofpower amplifier architectures. For example, advanced power trackingand/or envelop tracking techniques and/or architectures may be used inconjunction with at least one of the output power control circuit (520)and the frequency response compensation circuit (511).

Optionally, one or more part of the output power control circuit (520)and/or the frequency response compensation circuit (511) may becontrolled by a CMOS control. In such cases, the CMOS control may beconfigured to receive band and/or power mode controls over a MIPIdigital interface.

As illustrated in [0068] FIG. 11 all or at least a part of the poweramplification system (500) may be implemented in a module (300). Such amodule (300) may be, for example, a front-end module (FEM). In theexample of [0068] FIG. 11 , a module (300) may comprise a packagingsubstrate (302), and a number of components may be mounted on such apackaging substrate. For example, an Front-end Power ManagementIntegrated Circuit (FE-PMIC) component (304), a power amplifier assembly(306), a match component (308), and a duplexer assembly (310) may bemounted and/or implemented on and/or within the packaging substrate(302). The power amplifier assembly (306) may comprise at least a partof the frequency response compensation circuit (511) and/or at least apart of the output power control circuit (520), such as those describedabove with respect to [0059] FIG. 5 and [0060] FIG. 6 . The poweramplifier assembly (306) may include a push-pull amplifier and atransformer balun. Other components such as a number of SMT(surface-mount technology) devices (314) and an antenna switch module(ASM) (312) may also be mounted on the packaging substrate (302).Although all of the various components are depicted as being laid out onthe packaging substrate (302), it will be understood that somecomponent(s) can be implemented over other component(s).

In some implementations, a device and/or a circuit having one or morefeatures described herein may be included in an RF device such as awireless device. Such a device and/or a circuit may be implementeddirectly in the wireless device, in a modular form as described herein,or in some combination thereof. Such a wireless device may include, forexample, a cellular phone, a smart-phone, a hand-held wireless devicewith or without phone functionality, a wireless tablet, etc.

[0069] FIG. 12 illustrates an example wireless device (400) having oneor more advantageous features described herein. In the context of amodule having one or more features as described herein, such a modulemay be generally depicted by a dashed box 300, and can be implementedas, for example, a front-end module (FEM).

Referring to [0069] FIG. 12 , power amplifiers (PAs) (420) may receivetheir respective RF signals from a transceiver (410) that can beconfigured and operated in known manners to generate RF signals to beamplified and transmitted, and to process received signals. Thetransceiver (410) may interact with a baseband sub-system (408) that isconfigured to provide conversion between data and/or voice signalssuitable for a user and RF signals suitable for the transceiver (410).The transceiver (410) can also be in communication with a powermanagement component (406) that is configured to manage power for theoperation of the wireless device (400). Such power management can alsocontrol operations of the baseband sub-system (408) and the module(300). The baseband sub-system (408) may be connected to a userinterface (402) to facilitate various input and output of voice and/ordata provided to and received from the user. The baseband sub-system(408) may also be connected to a memory (404) that is configured tostore data and/or instructions to facilitate the operation of thewireless device, and/or to provide storage of information for the user.

In the example wireless device (400) shown in [0069] FIG. 12 , outputsof the PAs (420) may be matched via respective match circuits (422) androuted to their respective duplexers (424). Such amplified and filteredsignals may be routed to an antenna (416) through an antenna switch(414) for transmission. Optionally, the duplexers (424) may allowtransmit and receive operations to be performed simultaneously using acommon antenna (416). Received signals may be routed to “Rx” paths thatmay comprise, for example, a low-noise amplifier (LNA).

A number of other wireless device configurations may utilize one or morefeatures described herein. For example, a wireless device does not needto be a multi-band device. In another example, a wireless device mayinclude additional antennas such as diversity antenna, and additionalconnectivity features such as Wi-Fi, Bluetooth, and GPS.

As described herein, one or more features of the present disclosure mayprovide a number of advantages when implemented in systems such as thoseinvolving the wireless device of [0069] FIG. 12 . For example, thedisclosed architecture may greatly improve the usable bandwidth of apush-pull amplifier.

Unless the context clearly requires otherwise, throughout thedescription and the claims, the words “comprise,” “comprising,” and thelike are to be construed in an inclusive sense, as opposed to anexclusive or exhaustive sense; that is to say, in the sense of“including, but not limited to.” The word “coupled”, as generally usedherein, refers to two or more elements that may be either directlyconnected, or connected by way of one or more intermediate elements.Additionally, the words “herein,” “above,” “below,” and words of similarimport, when used in this application, shall refer to this applicationas a whole and not to any particular portions of this application. Wherethe context permits, words in the above Description using the singularor plural number may also include the plural or singular numberrespectively. The word “or” in reference to a list of two or more items,that word covers all of the following interpretations of the word: anyof the items in the list, all of the items in the list, and anycombination of the items in the list.

The above detailed description of embodiments of the invention is notintended to be exhaustive or to limit the invention to the precise formdisclosed above. While specific embodiments of, and examples for, theinvention are described above for illustrative purposes, variousequivalent modifications are possible within the scope of the invention,as those skilled in the relevant art will recognize. For example, whileprocesses or blocks are presented in a given order, alternativeembodiments may perform routines having steps, or employ systems havingblocks, in a different order, and some processes or blocks may bedeleted, moved, added, subdivided, combined, and/or modified. Each ofthese processes or blocks may be implemented in a variety of differentways. Also, while processes or blocks are at times shown as beingperformed in series, these processes or blocks may instead be performedin parallel, or may be performed at different times.

The teachings of the invention provided herein can be applied to othersystems, not necessarily the system described above. The elements andacts of the various embodiments described above can be combined toprovide further embodiments.

While some embodiments of the inventions have been described, theseembodiments have been presented by way of example only, and are notintended to limit the scope of the disclosure. Indeed, the novel methodsand systems described herein may be embodied in a variety of otherforms; furthermore, various omissions, substitutions and changes in theform of the methods and systems described herein may be made withoutdeparting from the spirit of the disclosure. The accompanying claims andtheir equivalents are intended to cover such forms or modifications aswould fall within the scope and spirit of the disclosure.

What is claimed is:
 1. A power amplification system comprising: a poweramplifier circuit; an output power control circuit that provides aplurality of values of capacitance, the output power control circuitincluding at least one load control capacitor coupled to a load controlswitch to control a value of the capacitance provided by the outputpower control circuit; and a balun coupled to the power amplifiercircuit and to the output power control circuit.
 2. The poweramplification system of claim 1 wherein the power amplifier circuitcomprises a push-pull amplifier.
 3. The power amplification system ofclaim 1 wherein at least two transistors of the power amplifier circuitare differential transistors.
 4. The power amplification system of claim3 wherein at least one of the at least two transistors is aheterojunction bipolar transistor.
 5. The power amplification system ofclaim 3 wherein the balun comprises a first coil having a first end anda second end, the first end of the first coil being coupled to a firstdifferential transistor and the second end of the first coil beingcoupled to a second differential transistor.
 6. The power amplificationsystem of claim 5 wherein the first end of the first coil is coupled toa drain or a collector of the first differential transistor and thesecond end of the first coil is coupled to a drain or a collector of thesecond differential transistor.
 7. The power amplification system ofclaim 1 wherein the balun comprises a second coil having a first end anda second end, the first end of the second coil being coupled to an RFoutput node and the second end of the second coil being coupled to aground.
 8. The power amplification system of claim 7 wherein the secondend of the second coil is coupled to the ground via one or moretermination capacitors.
 9. The power amplification system of claim 8wherein at least one of the one or more termination capacitors is asurface-mount capacitor.
 10. The power amplification system of claim 8wherein the output power control circuit is coupled with at least one ofthe one or more termination capacitors.
 11. The power amplificationsystem of claim 10 wherein at least one of the one or more load controlcapacitors and at least one of the one or more termination capacitorsare connected in parallel.
 12. The power amplification system of claim 8wherein a capacitance of the balun is dependent on one or more of: avalue of the one or more termination capacitors of the balun, a value ofthe capacitance provided by the output power control circuit, whetherthe one or more termination capacitors and the output power controlcircuit is connected in parallel or in series, and whether the loadcontrol switch is on or off.
 13. The power amplification system of claim1 wherein the output power control circuit provides low capacitancehaving a value close to zero when the load control switch is off. 14.The power amplification system of claim 1 wherein, when the load controlswitch is off, the output power control circuit does not provideadditional capacitance to the balun, and the power amplification systemhas a load impedance value that leads to a lower output power.
 15. Thepower amplification system of claim 1 wherein, when the load controlswitch is on, the output power control circuit provides additionalcapacitance to the balun, causing a load impedance value to decrease andoutput power of the power amplification system to increase to a higheroutput power.
 16. The power amplification system of claim 1 wherein thepower amplification system comprises and/or is connected to one or morepower amplifier components configured to provide at least one ofadvanced power tracking and envelop tracking.
 17. The poweramplification system of claim 1 wherein one or more part of the outputpower control circuit is controlled by a CMOS control, the CMOS controlbeing configured receive band and/or power mode controls over a MIPIdigital interface.
 18. The power amplification system of claim 1comprising a frequency response compensation circuit that provides aplurality of values of capacitance, the frequency response compensationcircuit including at least one tuning capacitor coupled to a switch tocontrol a value of the capacitance provided by the frequency responsecompensation circuit, and the frequency response compensation circuitbeing coupled to at least two transistors of the power amplifiercircuit, the frequency response compensation circuit configured toreduce variation over frequency of a load impedance of the poweramplification system.
 19. A wireless device comprising: a memory; a userinterface; a baseband sub-system; a transceiver; a power managementcomponent; and a power amplification system, the power amplificationsystem including a power amplifier circuit, an output power controlcircuit that provides a plurality of values of capacitance, the outputpower control circuit having at least one load control capacitor coupledto a load control switch to control a value of the capacitance providedby the output power control circuit, and a balun coupled to the poweramplifier circuit and to the output power control circuit.
 20. Awireless module comprising: a packaging substrate; one or moresurface-mount devices; a duplexer assembly; a front-end power managementintegrated circuit; a match component; an antenna switch module; and apower amplifier assembly including a power amplification system, thepower amplification system having a power amplifier circuit, and anoutput power control circuit providing a plurality of values ofcapacitance, the output power control circuit having at least one loadcontrol capacitor coupled to a load control switch to control the valueof the capacitance provided by the output power control circuit, and abalun coupled to the power amplifier circuit and to the output powercontrol circuit.